This invention relates generally to enhancing reliability of a digital design, and more particularly to enhancing reliability on scan-initialized latches that affect functionality in a digital design.
As digital design, such as a microprocessor, becomes more complex, alternate modes of operation may be desirable to bypass complicated sequences. Therefore, these designs usually include scan-initialized latches, are commonly known as disable switches, chicken switches, back-off mode switches or simply mode latches. The mode latches act as switches, holding an assigned state value, to modify functionality within the designs by enabling or disabling circuitry with which they interface. The mode latches cannot change states using normal functional logic or circuits, but can be changed during system initialization through a process known as scanning. This is intended to provide a window of access to configure and test the design, and prevent potentially unintended or harmful changes of these mode latches from occurring after initialization. These mode latches default to a state such that the design behaves as planned for best performance and for providing maximum functionality. Configuring a design for best performance with maximum functionality can lead to complex windows, where the design becomes very bug prone.
When the mode latches are scanned into non-default (active) states, design performance can change, resulting in modified behavior. The affected design may respond by disabling a feature, removing some performance enhancements, working with reduced capacity, or simply running at some preset “slower” modes. During verification of actual hardware or its design model, certain design bugs can be encountered in complicated design windows. Sometimes developing an actual fix to the identified bugs can require a long turnaround time. The most important role of the latches is to provide an alternate functional behavior for temporarily workarounds. If a certain workaround switch is available by simply changing a mode latch's initial state, so to avoid the complex window that leads to a design bug, verification can progress until a final fix is available.
In a microprocessor or any complex design that provides best of breed error detection, various approaches may be devised to check for or prevent possible errors caused by single event upsets. A single event upset (SEU) is a change of state caused by a high-energy particle strike to a sensitive node in a micro-electronic device that may result from environmental effects, such as alpha particles. Although it is intended for scan-initialized latches to retain their values during normal operation, and numerous of circuit design techniques had been devised to harden these latches, SEUs can still result in the mode latches changing state unexpectedly. It would be beneficial to develop an approach to cover potential unintended activation of scan-initialized mode latches that can lead to unwanted modifications of the design functionality.
To detect if any of the mode latches have been activated unintentionally during normal operation, one approach is to include parity latch bits covering these latches. If any of the mode latches flip, a parity error is detected, and the design can be re-scanned. However, a reboot or system initialization, which is usually employed to re-scan the mode latches, is not a good option. This kind of interruption is not desirable for a processor running in a server that needs to provide seamless operation. On a processor that includes a hardware recovery scheme, a general state reset cannot restore the scan-initialized latches either. In turn, the recovery will fail, and in some high reliability systems, another processor may be used to pick up the current process being executed. Even though that solution may be acceptable, it is not generally available and is quite complex to implement.
It would be desirable to increase overall reliability of a digital design that uses scan-initialized latches that can affect functionality during normal operation. The solution should be simple to reduce cost and minimize the associated burden during normal operation. Accordingly, there is a need in the art for enhancing reliability on scan-initialized latches that affect functionality in a digital design.